• DocumentCode
    3401647
  • Title

    A multioperand two´s complement addition algorithm

  • Author

    Kobayashi, Hideaki

  • Author_Institution
    Department of Electrical and Computer Engineering University of South Carolina Columbia, SC 29208
  • fYear
    1985
  • fDate
    4-6 June 1985
  • Firstpage
    16
  • Lastpage
    19
  • Abstract
    This paper presents a novel algorithm for summing a set of 2´s complement numbers in parallel. The 2´s complement addition is converted to an equivalent parallel summation of unsigned numbers. The conversion is performed by simply complementing all the sign bits. Only a few constant bits are required for sign correction. This algorithm is suitable for computer-aided design (CAD) of custom VLSI.
  • Keywords
    Adders; Algorithm design and analysis; Computers; Design automation; Layout; Logic gates; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic (ARITH), 1985 IEEE 7th Symposium on
  • Conference_Location
    Urbana, IL,
  • Type

    conf

  • DOI
    10.1109/ARITH.1985.6158958
  • Filename
    6158958
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3401647