A BCH decoding architecture with mixed parallelization degrees for flash controller applications

Error correction coding (ECC) has become one of the most important tasks of flash memory controllers. The gate count of ECC hardware is taking up a significant share of the overall SOC logic. Scaling ECC strength to growing error correction requirements has become increasingly difficult when considering cost and area limitations. In this work, a new BCH decoding architecture is presented that combines different parallelization degrees for the Berlekamp-Massey algorithm and the Chien search. This approach significantly reduces the number of required multipliers. Nevertheless, the average decoding speed is equal to that of a fully parallel implementation.