New methods for parallel pattern fast fault simulation for synchronous sequential circuits

The paper describes COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED results from coupling a parallel pattern simulator with a nonparallel simulator both working based on single fault propagation. Circuit partitioning and removing all feedback loops implemented into the parallel part of COMBINED result in a reduction of the number of events. In addition, the nonparallel part of COMBINED has been expanded either to detect more faults by introducing restricted symbolic fault simulation, or to reduce the number of events using PStar Algorithm which are also presented. COMBINED runs substantially faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator.