Reliable transform domain adaptive filters designed with a hybrid combination of redundant hardware modules and algorithmic error detection and correction

System architectures for fault tolerant computing and signal processing can be based on either modular hardware redundancy or arithmetic error detection and correction coding. Traditional triple modular redundancy (TMR) is very general but often leads to hardware intensive high-power implementations. In contrast, fault tolerant designs that rely on arithmetic coding reduce hardware requirements but result in higher computational requirements that must be implemented in a separate decoding unit. This paper proposes a hybrid combination of redundant hardware modules and arithmetic (algorithmic) error detection to produce efficient and reliable designs for transform domain adaptive filters.