A 1.4 Gbit/s CMOS driver for 50 Ω ECL systems

Author

Navarro S., J. ; Silveira, Reinaldo ; Romao, Fãbio L. ; Van Noije, Wilhelmus A M

Author_Institution

Lab. de Sistemas Integraveis, Sao Paulo Univ., Brazil

fYear

1997

fDate

13-15 Mar 1997

Firstpage

14

Lastpage

18

Abstract

This paper presents an output buffer which converts CMOS into ECL levels, and a brief analysis of its speed performance. The structure is designed in a 0.8 μm CMOS process (effective length is 0.7 μm). The circuit operation is based on current source switching. In the speed analysis we show that the speed is severely limited by the output load, and that the process, for common applications, is a secondary factor. Experimental results for the buffer operating at 1.4 Gbit/s rate are shown. The circuit is part of a 1.2 Gbit/s SDH/SONET system

Keywords

CMOS logic circuits; SONET; buffer circuits; driver circuits; emitter-coupled logic; integrated circuit design; switched current circuits; synchronous digital hierarchy; very high speed integrated circuits; 0.7 mum; 0.8 mum; 1.4 Gbit/s; 50 ohm; CMOS driver; CMOS-ECL convertor output buffer; ECL systems; SDH/SONET system; circuit operation; current source switching; effective length; output buffer; output load; speed performance; CMOS integrated circuits; Circuit optimization; Circuit simulation; Distributed parameter circuits; Driver circuits; Inverters; Packaging; Parasitic capacitance; Resistors; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1997. Proceedings. Seventh Great Lakes Symposium on

Conference_Location

Urbana-Champaign, IL

ISSN

1066-1395

Print_ISBN

0-8186-7904-2

Type

conf

DOI

10.1109/GLSV.1997.580404

Filename

580404