• DocumentCode
    3409263
  • Title

    A new method for asynchronous pipeline control

  • Author

    Appleton, Sam S. ; Morton, Shannon V. ; Liebelt, Michael J.

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
  • fYear
    1997
  • fDate
    13-15 Mar 1997
  • Firstpage
    100
  • Lastpage
    104
  • Abstract
    We explore the potential for enhanced performance in asynchronous pipelines by the elimination of unnecessary signalling from the critical path, thus making the common case fast. An improvement of 15% over an optimal two-phase signalling approach for both static and dynamic logic control is demonstrated. We describe extensions to the approach that add functionality with no cycle time overhead
  • Keywords
    CMOS logic circuits; VLSI; asynchronous circuits; pipeline processing; VLSI architecture; asynchronous pipeline control; dynamic logic control; flow controlled asynchronous method; static logic control; Computational modeling; Control systems; Degradation; Delay effects; Logic; Optical signal processing; Optimal control; Pipelines; Propagation delay; Protocols;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1997. Proceedings. Seventh Great Lakes Symposium on
  • Conference_Location
    Urbana-Champaign, IL
  • ISSN
    1066-1395
  • Print_ISBN
    0-8186-7904-2
  • Type

    conf

  • DOI
    10.1109/GLSV.1997.580418
  • Filename
    580418
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3409263