Power efficient data retention logic design in the integration of power gating and clock gating

Recently, integration of power gating (PG) and clock gating (CG) has been proposed to reduce dynamic power and active leakage power simultaneously. During the integration, data retention logics are inserted between the power-gated cells and non-power-gated cells to hold power-gated data so that the operations of the non-power-gated cells function correctly. It is very important that the power consumption of the data retention logic should be very small so that the power reduction by CG and PG is not offset too much. Although there are several data retention flip-flop designs in the traditional PG design, no specific data retention logic design has been proposed during the integration of PG and CG. In this paper, a low power data retention logic design is proposed to fill this gap. The experimental results on ten ISCAS´85 benchmark circuits show that the power of our data retention logic design is only 1.58% of the power savings on average.