DocumentCode
3409860
Title
FV encoding for low-power data I/O
Author
Yang, Juri ; Gupta, Rajiv
Author_Institution
Dept. of Comput. Sci., Arizona Univ., Tucson, AZ, USA
fYear
2001
fDate
2001
Firstpage
84
Lastpage
87
Abstract
The power consumed by I/O pins of a CPU is significant due to high capacitances associated with the pins. While highly effective techniques for reducing address bus switching exist, similarly effective techniques for data bus have not been developed. We have discovered a characteristic of values transmitted over the data bus according to which a small number of distinct values, called frequent values, account for 58-68% of transmissions over the external data bus. To exploit this characteristic we have developed a method for dynamic identification of frequent values and their use in encoding data values using FV (frequent value) encoding scheme. Our experiments show that FV encoding of 32 frequent values yields an average reduction of 42.7% (with onchip data cache) and 67.63% (without on-chip data cache) in data bus switching activity for SPEC95 benchmarks
Keywords
encoding; low-power electronics; system buses; CPU; I/O pin capacitance; frequent value encoding; low-power data bus; switching activity; Capacitance; Central Processing Unit; Circuits; Computer science; Data buses; Encoding; Permission; Pins;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, International Symposium on, 2001.
Conference_Location
Huntington Beach, CA
Print_ISBN
1-58113-371-5
Type
conf
DOI
10.1109/LPE.2001.945379
Filename
945379
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