An algorithm-hardware-system approach to VLIW multimedia processors

Author

Kneip, Johannes ; Berekovic, Mladen ; Pirsch, Peter

Author_Institution

Lab. fur Inf. Technol., Hannover Univ., Germany

fYear

1997

fDate

23-25 Jun 1997

Firstpage

433

Lastpage

438

Abstract

A number of recently published DSPs and multimedia processors emphasize on Very Long Instruction Word (VLIW) architectures to achieve flexibility, processing power and high-level language programmability needed for future multimedia applications. In this paper we show that exclusive exploitation of instruction level parallelism decreases in efficiency as the degree of parallelism increases. This is mainly caused by algorithm characteristics, VLSI design and compiler restrictions. We discuss selected aspects from these fields and possible solutions to upcoming bottlenecks from a practical point of view

Keywords

digital signal processing chips; instruction sets; multimedia systems; parallel architectures; DSPs; VLIW multimedia processors; VLSI design; algorithm-hardware-system approach; compiler restrictions; flexibility; high-level language programmability; instruction level parallelism; multimedia processors; processing power; very long instruction word architectures; Algorithm design and analysis; Centralized control; Clocks; Communication system control; Control systems; Costs; Multiprocessing systems; Parallel processing; VLIW; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Multimedia Signal Processing, 1997., IEEE First Workshop on

Conference_Location

Princeton, NJ

Print_ISBN

0-7803-3780-8

Type

conf

DOI

10.1109/MMSP.1997.602673

Filename

602673