A 0.18 μm 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

Author

Cho, Woo Yeong ; Cho, Beak-Hyung ; Choi, Byung-Gil ; Oh, Hyung-Rok ; Kang, Sang-beom ; Kim, Ki-Sung ; Kim, Kyung-Hee ; Kim, Du-Eung ; Kwak, Choong-Keun ; Byun, Hyun-Geun ; Hwang, Young-nam ; Ahn, Su-jin ; Jung, Gi-tae ; Jung, Hong-sik ; Kim, Kinam

Author_Institution

Samsung Electron., Hwasung, South Korea

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

40

Abstract

A non-volatile 64 Mb phase-transition RAM is developed by fully integrating a chalcogenide alloy GST (Ge₂Sb₂Te₅) into 0.18 μm CMOS technology. This alloy is programmed by resistive heating. To optimize SET/RESET distribution, a 512 kb sub-core architecture, featuring meshed ground line, is proposed. Random read access and write access for SET/RESET are 60 ns, 120 ns and 50 ns, respectively, at 3.0 and 30°C.

Keywords

CMOS memory circuits; chalcogenide glasses; germanium compounds; integrated circuit design; integrated circuit interconnections; integrated memory circuits; memory architecture; random-access storage; resistance heating; solid-state phase transformations; ternary semiconductors; 0.18 micron; 120 ns; 3.0 V; 50 ns; 512 kbit; 60 ns; 64 Mbit; CMOS technology integration; Ge₂Sb₂Te₅; Ge₂Sb₂Te₅ chalcogenide alloy; PRAM; SET/RESET distribution optimization; meshed ground line; nonvolatile phase-transition random-access memory; phase-transition RAM; random read access; resistive heating programmed alloy; sub-core architecture; write access; CMOS technology; Conductivity; Degradation; Driver circuits; Nonvolatile memory; Phase change random access memory; Random access memory; Threshold voltage; Tin alloys; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332583

Filename

1332583