An experimental 256 Mb non-volatile DRAM with cell plate boosted programming technique

Author

Ahn, J.-H. ; Hong, S.-H. ; Kim, S.-J. ; Ko, J.-B. ; Shin, S.-W. ; Lee, S.-D. ; Kim, Y.-W. ; Lee, K.-S. ; Lee, S.-K. ; Jang, S.-E. ; Choi, J.-H. ; Kim, S.-Y. ; Bae, G.-H. ; Park, S.-W. ; Park, Y.-J.

Author_Institution

Hynix Semicond., Icheon, South Korea

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

42

Abstract

A 256 Mb NVDRAM is fabricated with a modified 0.115 μm DRAM process. The cell transistor has a scaled polysilicon-oxide-nitride-oxide-silicon (SONOS) structure that traps electrons or holes at a relatively low voltage stress. NVDRAM utilizes DRAM storage node boost from the cell plate for programming to ensure more reliable operation.

Keywords

DRAM chips; PLD programming; dielectric thin films; elemental semiconductors; integrated circuit interconnections; integrated circuit reliability; interface structure; microprogramming; silicon; silicon compounds; 0.115 micron; 256 Mbit; DRAM storage node boost; NVDRAM; SONOS structure; Si-SiO₂-Si₃N₄-SiO₂-Si; cell plate boosted programming technique; cell transistor; electron trapping; hole trapping; modified DRAM process; nonvolatile DRAM; reliable operation; scaled polysilicon-oxide-nitride-oxide-silicon structure; voltage stress; Batteries; Capacitors; Flash memory; Hot carriers; Mobile computing; Nonvolatile memory; Random access memory; SONOS devices; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332584

Filename

1332584