• DocumentCode
    341161
  • Title

    Multistage interconnection networks for k/n rate Viterbi decoders

  • Author

    Akopian, David ; Takala, Jarmo ; Astola, Jaakko ; Saarinen, Jukka

  • Author_Institution
    Signal Process. Lab., Tampere Univ. of Technol., Finland
  • Volume
    2
  • fYear
    1998
  • fDate
    1998
  • Firstpage
    845
  • Abstract
    New parallel architectures are proposed for Viterbi (1967) decoders with the possibility of a trade-off between the complexity and the speed. This work generalizes the design of decoders with a code rate of 1/n reported for k/n rate codes corresponding to high radix systems with the number of states N=rn, r>2. Two different solutions are given. Finally, the family of architectures is derived systematically for the general case of k/n rate codes
  • Keywords
    Viterbi decoding; computational complexity; multistage interconnection networks; parallel architectures; Viterbi decoders; code rate; complexity; decoder design; high radix systems; multistage interconnection networks; parallel architectures; speed; Laboratories; Markov processes; Maximum likelihood decoding; Maximum likelihood estimation; Multiprocessor interconnection networks; Parallel architectures; Shift registers; Signal processing; Signal processing algorithms; Viterbi algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Global Telecommunications Conference, 1998. GLOBECOM 1998. The Bridge to Global Integration. IEEE
  • Conference_Location
    Sydney,NSW
  • Print_ISBN
    0-7803-4984-9
  • Type

    conf

  • DOI
    10.1109/GLOCOM.1998.776852
  • Filename
    776852
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=341161