An algorithm for multiplication module (2/sup n/+1)

This paper presents a new method for modulo (2/sup n/+1) multiplication. Existing algorithms either use recursive module (2/sup n/+1) addition, or a regular binary multiplication integrated with the module reduction operation. Although suitable for large n, this latter approach requires conversions between diminished-1 and binary representations. We propose a parallel algorithm for module (2/sup n/+1) multiplication which does not require any conversions. The algorithm applies a Wallace (1964) tree, resulting in a considerably improved multiplication speed. Module (2/sup n/+1) multipliers built using this new algorithm exhibit an extremely modular structure, which suggests advantages for VLSI implementation.