A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump

Author

Huh, Hyungki ; Koo, Yido ; Lee, Kang-Yoon ; Ok, Yeonkyeong ; Lee, Sungho ; Kwon, Daehyun ; Lee, Jeongwoo ; Park, Joonbae ; Lee, Kyeongho ; Jeong, Deog-Kyoon ; Kim, Wonchan

Author_Institution

Seoul Nat. Univ., South Korea

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

100

Abstract

A fully integrated dual-band frequency synthesizer in 0.35 μm CMOS technology achieves a phase noise of -141 dBc/Hz at 1.25 MHz offset in the PCS band with a reference frequency doubler. Fractional spurs are reduced by 8.6 dB at 50 kHz offset with a replica compensated charge pump.

Keywords

CMOS integrated circuits; cellular radio; compensation; frequency multipliers; frequency synthesizers; integrated circuit measurement; integrated circuit noise; personal communication networks; phase noise; reference circuits; 0.35 micron; CMOS dual-band fractional-n synthesizer; CMOS technology; PCS band; dual-band frequency synthesizer; fractional spurs; frequency offset; phase noise; reference doubler; reference frequency doubler; replica compensated charge pump; 1f noise; Charge pumps; Dual band; Frequency; Phase locked loops; Phase noise; Quantization; Sampling methods; Semiconductor device noise; Synthesizers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332613

Filename

1332613