High speed 0.1 /spl mu/m dual gate CMOS with low energy phosphorus/boron implantation and cobalt salicide

Author

Hori, A. ; Umimoto, H. ; Nakaoka, H. ; Sekiguchi, M. ; Segawa, M. ; Arai, M. ; Takase, M. ; Kanda, A.

Author_Institution

Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Moriguchi, Japan

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

575

Lastpage

578

Abstract

A novel dual gate CMOS with low energy phosphorus/boron implantation and cobalt salicide is proposed. This technology suppresses boron penetration for pMOS, while maintaining high current drivability for nMOS with simple process steps. In addition, the drain junction capacitance of nMOS is drastically decreased, compared to a conventional MOSFET with arsenic source/drain. The delay time of CMOS ring oscillator was 28 ps, which is due to low junction capacitance and high current driving capability.

Keywords

CMOS integrated circuits; boron; capacitance; integrated circuit metallisation; integrated circuit technology; ion implantation; phosphorus; 0.1 micron; B penetration suppression; CoSi/sub 2/; NMOS drain junction capacitance; Si:B; Si:P; high current drivability; high speed dual gate CMOS; junction capacitance reduction; low energy B implantation; low energy P implantation; Boron; CMOS process; CMOS technology; Capacitance; Cobalt; Fabrication; Germanium; Impurities; Leakage current; MOS devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.554049

Filename

554049