DocumentCode
3412783
Title
A 2Gb/s point-to-point heterogeneous voltage capable DRAM interface for capacity-scalable memory subsystems
Author
Kennedy, Jessie ; Ellis, Ryan ; Jaussi, James ; Mooney, Randy ; Borkar, Shekhar ; Jung-Hwan Choi ; Jae-Kwan Kim ; Chan-Kyong Kim ; Woo-Seop Kim ; Chang-Hyun Kim ; Soo-In Cho ; Loeffler, Steffen ; Hoffmann, J. ; Hokenmaier, Wolfgang ; Houghton, R. ; Vogels
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
214
Abstract
We describe a DRAM interface operating at 2Gb/s/pin. It utilizes simultaneous bidirectional signaling in a daisy-chained, point-to-point configuration to enable scalable memory subsystems, and also provides direct attach capability for logic devices. We present results from a system using both logic and DRAM test-chips.
Keywords
CMOS memory circuits; DRAM chips; clocks; timing jitter; 2 Gbit/s; DRAM interface; capacity-scalable memory subsystems; clocking strategy; daisy-chained point-to-point configuration; direct attach capability; jitter accumulation; point-to-point heterogeneous voltage capability; simultaneous bidirectional signaling; Bandwidth; Clocks; Delay; Differential amplifiers; Jitter; Network topology; Random access memory; Signal processing; Transmitters; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332670
Filename
1332670
Link To Document