On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology

Author

Ker, Ming-Dou ; Chung-Yu Wu ; Cheng, Tao ; Wu, Chung-Yu ; Yu, Ta-Lee

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1995

fDate

18-22 Sep 1995

Firstpage

135

Lastpage

138

Abstract

Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC´s can be significantly improved

Keywords

CMOS integrated circuits; current distribution; electrostatic discharge; integrated circuit reliability; protection; 0.5 micron; 3 V; CMOS IC; ESD protection circuits; NMOS devices; PMOS devices; capacitor-couple technique; onchip ESD protection; snapback voltage reduction; submicron CMOS technology; uniform ESD current distribution; CMOS integrated circuits; Capacitance; Capacitors; Coupling circuits; Current distribution; Electrostatic discharge; MOS devices; Protection; Robustness; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580699

Filename

580699

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3412926