Multiprocessor memory management: integrating four-address virtual memory and aliased page tables

Memory management in multiprocessors is currently a lively area for research. Many research efforts have addressed the complexities of maintaining consistency among shared variables in a distributed shared memory. We are instead seeking to develop an overarching memory architecture that mimics techniques evolved by humans for similar tasks, while avoiding the potentially severe performance penalties associated with memory architectures that ignore inherent efficiencies in the underlying hardware architecture. Four-address virtual memory provides sufficient degrees of freedom in the address translation process to support nearly any desired sharing scheme. Aliased page tables provide an efficient mechanism for managing the copy-on-write “sharing” associated with some multiprocessor memory architectures. The combination yields a powerful multiprocessor memory management scheme that is capable of efficiently using underlying hardware facilities