DocumentCode
3413027
Title
A 43Gb/s 2:1 selector IC in 90nm CMOS technology
Author
Yamamoto, Takayuki ; Horinaka, M. ; Yamazaki, D. ; Nomura, Hideyuki ; Hashimoto, Koji ; Onodera, Hidetoshi
Author_Institution
Fujitsu Labs. Ltd., Kawasaki, Japan
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
238
Abstract
The 2:1 selector IC consists of three stages of input buffers, a 2:1 selector stage, and two stages of output buffers. By using multiple inductive peaking and selector architecture to suppress interference, the proposed circuit operates at a data rate of 43Gb/s and it is implemented in 90nm CMOS technology with 48nm transistors.
Keywords
CMOS logic circuits; buffer circuits; current-mode logic; high-speed integrated circuits; multiplexing equipment; 43 Gbit/s; 90 nm; CMOS technology; current-mode logic; differential amplifier; frequency response; high-bandwidth data communication; high-speed operation; input buffers; multiple inductive peaking; output buffers; parasitic resistance; selector IC; Bandwidth; CMOS integrated circuits; CMOS technology; Cutoff frequency; Inductors; Multiplexing; Parasitic capacitance; Tail; Transconductors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332682
Filename
1332682
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