DocumentCode
3413106
Title
A single-chip, asynchronous echo canceller for high-speed data communication
Author
Mackey, Richard P. ; Rodríguez, Jeffrey J. ; Carothers, Jo Dale ; Vrudhula, Sarma B K
Author_Institution
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
fYear
1995
fDate
18-22 Sep 1995
Firstpage
181
Lastpage
184
Abstract
A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz
Keywords
FIR filters; adaptive filters; asynchronous circuits; data communication; data communication equipment; echo suppression; least mean squares methods; 205 kHz; LMS algorithm; adaptive FIR filter; high-speed data communication; pipelined circuit; single-chip asynchronous echo canceller; Adaptive filters; Clocks; Data communication; Delay; Digital filters; Echo cancellers; Finite impulse response filter; Hardware; Least squares approximation; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location
Austin, TX
ISSN
1063-0988
Print_ISBN
0-7803-2707-1
Type
conf
DOI
10.1109/ASIC.1995.580710
Filename
580710
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