Performance analysis of parallel ATM connections for gigabit speed applications

A system which uses multiple asynchronous transfer mode (ATM) virtual circuits operating in parallel in order to control two WAN hosts at gigabit speeds is studied. Packets in parallel channels can bypass each other, so reordering of packets before delivery to the host is required. Performance parameters of this system, including ATM channel delay, packet loss, and resequencing delay, are analyzed, using a model for an ATM channel that multiplexes ATM virtual circuits carrying bursty and nonbursty traffic. It is found that the mean and variance of packet delay through an ATM switch grow linearly with burst size, and that the delay distribution can be closely approximated by a normal distribution. It is shown that packet loss is log-linear in the ratio of buffer size to burst size, and for maximum bursts larger than 50 cells, a buffer size of twice the maximum burst size is sufficient to achieve packet loss probabilities less than 10^-9. Resequencing delay is shown to be insensitive to burst size, but the variance is large and grows linearly with burst size