DocumentCode
3413387
Title
Design, verification, and validation of self-checking software components
Author
Geoghegan, J. ; Avresky, Dimiter
Author_Institution
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
fYear
1996
fDate
27-29 Mar 1996
Firstpage
420
Lastpage
426
Abstract
We propose a formal approach for adding fault detection to software. An assertion-based formalism is used to represent specifications and verify completeness and consistency. This specification is used to generate a flow graph, which is used to construct an exemplar-path tree. This representation is then used to generate an input set to exercise and verify the implementation. Previous software fault-tolerance (SFT) techniques emphasized algorithm-based fault tolerance (ABFT) which focused on detecting hardware faults that corrupted data structure contents. We propose a method that also detects hardware faults, which cause program flow errors. Our technique embeds two types of software checks. The first is based on the ABFT techniques described in the literature. The second type of check is used to detect faults that cause program flow errors. The exemplar-path tree provides information that can be used to predict a future program location, given the current location. During execution, program locations are recorded, along with expected locations, as determined from the exemplar-path tree. This information then is used to verify, that the future location is executed as expected. Hardware fault coverage has been estimated through experiments with the fault injection tool, SOFIT. Faults of differing durations were injected into memory, address bus, data bus, and CPU registers. The data presented, demonstrate the effectiveness of the method for detecting hardware faults
Keywords
fault tolerant computing; formal specification; program verification; software fault tolerance; system buses; tree data structures; CPU registers; SOFIT fault injection tool; address bus; assertion-based formalism; completeness verification; consistency verification; data bus; data structure content corruption; exemplar-path tree; fault detection; flow graph; formal approach; future program location prediction; hardware fault coverage; hardware fault detection; input set; program flow errors; self-checking software component design; self-checking software component validation; self-checking software component verification; software fault-tolerance techniques; specifications; Computer errors; Data structures; Embedded software; Fault detection; Fault tolerance; Flow graphs; Hardware; Registers; Software algorithms; Tree graphs;
fLanguage
English
Publisher
ieee
Conference_Titel
Computers and Communications, 1996., Conference Proceedings of the 1996 IEEE Fifteenth Annual International Phoenix Conference on
Conference_Location
Scottsdale, AZ
Print_ISBN
0-7803-3255-5
Type
conf
DOI
10.1109/PCCC.1996.493666
Filename
493666
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