DocumentCode
3414076
Title
Timing uncertainty measurements on the Power5 microprocessor
Author
Restle, P.J. ; Franch, R.L. ; James, N.K. ; Huott, W.V. ; Skergan, T.M. ; Wilson, S.C. ; Schwartz, N.S. ; Clabes, J.G.
Author_Institution
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
354
Abstract
On-chip timing measurement (Skitter) circuits are included on the Power5 microprocessor. By cross-coupling the 3 Skitter instances, the combined effect of jitter, skew, and supply noise can be measured for all cycles of a pattern or an application. System results show a maximum of 27ps timing impact on a 500ps path.
Keywords
clocks; delay lock loops; digital phase locked loops; integrated circuit measurement; integrated circuit noise; measurement uncertainty; microprocessor chips; synchronisation; timing jitter; PLL jitter; Power5 microprocessor; Skitter circuits; clock distribution latency; clock distribution skew; on-chip timing measurement; register-tapped delay-line; supply noise; timing uncertainty measurement; Circuit noise; Clocks; Delay; Jitter; Latches; Measurement uncertainty; Microprocessors; Power supplies; Semiconductor device measurement; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332740
Filename
1332740
Link To Document