• DocumentCode
    3414137
  • Title

    A 10b 250MS/s binary-weighted current-steering DAC

  • Author

    Steyaert, M.

  • fYear
    2004
  • fDate
    15-19 Feb. 2004
  • Firstpage
    362
  • Abstract
    A 10b binary-weighted current-steering DAC has over 60dB SFDR at 250 MS/s for signals from DC to Nyquist. The chip draws 4mW from a dual 1.5/1.8V supply (plus load currents). Active area is less than 0.35 mm2 in a standard 0.18μm 1P5M 1.8V CMOS process, and both INL and DNL are below 0.1LSB.
  • Keywords
    CMOS integrated circuits; digital-analogue conversion; low-power electronics; 1.5 V; 1.8 V; CMOS process; SFDR; binary weighted current-steering DAC; buffer-latch-switch cell; differential output currents; dynamic performance; glitch energy; highly regular structure; low power consumption; segmented structure; CMOS process; Calibration; Current supplies; Decoding; Energy consumption; Frequency; Linearity; Mirrors; Semiconductor device measurement; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8267-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.2004.1332744
  • Filename
    1332744
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3414137