Design of a super-pipelined Viterbi decoder

This paper presents a novel super-pipelined VLSI architecture for Viterbi decoders. This architecture is capable of achieving high throughput in an area-efficient manner and hence it is an attractive architecture for implementing the Viterbi decoder where a large constraint length and high throughput rate are required. The throughput can be linearly increased by increasing the number of basic process elements. The notable advantage is its regularity and flexibility. A Viterbi decode (R=1/2 K=10) is designed in 0.6 μm 3.3 V CMOS process to demonstrate the favourable performance of this new architecture