DocumentCode
3414891
Title
A digitally enhanced 1.8 V 15 b 40 MS/s CMOS pipelined ADC
Author
Siragusa, E. ; Galton, Ian
Author_Institution
Univ. of California San Diego, La Jolla, CA, USA
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
452
Abstract
A 1.8 V 15 b 40 MS/s CMOS pipelined ADC with 90 dB SFDR and 72 dB peak SNR over the full Nyquist band is described. ADC performance is enhanced by digital background calibration of DAC noise and interstage gain error. The IC is realized in a 0.18 μm CMOS process, consumes 400 mW, and has a die size of 4 mm×5 mm.
Keywords
CMOS integrated circuits; analogue-digital conversion; calibration; error analysis; integrated circuit measurement; integrated circuit noise; pipeline processing; 0.18 micron; 1.8 V; 15 bit; 4 mm; 400 mW; 5 mm; ADC performance; CMOS process; DAC noise; IC power consumption; Nyquist band; SFDR; die size; digital background calibration; digitally enhanced CMOS pipelined ADC; interstage gain error; peak SNR; Additive noise; CMOS process; Calibration; Capacitors; Digital signal processing; High-resolution imaging; Logic; Low voltage; Noise cancellation; Pipelines;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332789
Filename
1332789
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