Obsolete integrated circuit replacement methodology using advanced electronic design automation technology

A methodology is proposed which encompasses the design, simulation, synthesis and layout of obsolete digital parts using EDA technologies that are currently available to cutting edge ASIC and FPGA designers. The approach described herein provides a means for exploiting the efficiencies afforded by design automation technologies, while meeting the functional performance, timing and area requirements of obsolete designs. In addition, a methodology for integrating multiple designs on one die is presented which reduces cost and maximizes gate density for small obsolete designs. This paper outlines in detail how functional, timing and layout requirements for obsolete parts can be met specifically using Hardware Description Languages (HDL) and advanced Electronics Design Automation (EDA) Tools from Mentor Graphics, Synopsys and Cascade Design Automation