A Single Chip Implementation of AES Cipher and Whirlpool Hash Function

Author

Kochar, Tarun ; Nandi, Sukumar ; Biswas, Santosh

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Guwahati, India

fYear

2009

fDate

18-20 Dec. 2009

Firstpage

1

Lastpage

4

Abstract

Advanced Encryption Standard (AES) is adopted as the standard for symmetric key cryptosystem. Hash functions are used as building blocks in various cryptographic applications. Whirlpool is one of the best known hash function reported in the literature. Many hardware based implementations of AES and Whirlpool have been proposed on separate chips. This paper presents an efficient hardware design for the AES and Whirlpool algorithm on a single chip which reduces the overall chip area. The design is implemented in Verilog and synthesized using Xilinx ISE 10.1.

Keywords

cryptography; hardware description languages; logic design; microprocessor chips; AES cipher; Verilog; Whirlpool hash function; Xilinx ISE 10.1; advanced encryption standard; cryptograpy; hardware design; single chip implementation; symmetric key cryptosystem; Application specific integrated circuits; Cryptography; Data security; Field programmable gate arrays; Hardware; Information security; Matrices; NIST; Pipeline processing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

India Conference (INDICON), 2009 Annual IEEE

Conference_Location

Gujarat

Print_ISBN

978-1-4244-4858-6

Electronic_ISBN

978-1-4244-4859-3

Type

conf

DOI

10.1109/INDCON.2009.5409426

Filename

5409426