DocumentCode
3414948
Title
A 12 b 80 MS/s pipelined ADC with bootstrapped digital calibration
Author
Grace, C.R. ; Hurst, Paul J. ; Lewis, Stephen H.
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
460
Abstract
A 12 b 80 MS/s pipelined ADC is calibrated for constant and signal-dependent gain errors as well as for slew-rate errors. With foreground calibration, peak SNDR is 72.6 dB, and peak SFDR is 85.4 dB. Using an on-chip microprocessor for calibration, the total power dissipation is 755 mW from 2.5 V, and the active area is 19.6 mm2 in a 0.25 μm CMOS process.
Keywords
CMOS integrated circuits; analogue-digital conversion; calibration; error analysis; integrated circuit measurement; integrated circuit noise; microprocessor chips; pipeline processing; 0.25 micron; 12 bit; 2.5 V; 755 mW; CMOS process; active area; bootstrapped digital calibration; constant gain errors; foreground calibration; on-chip microprocessor; peak SNDR; pipelined ADC; signal-dependent gain errors; slew-rate errors; total power dissipation; Calibration; Computer errors; Engines; Gain; Linearity; Microprocessors; Prototypes; Signal processing; Testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332793
Filename
1332793
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