DocumentCode
341496
Title
Routing chip based on a modified trie for ATM, IP and Ethernet
Author
Torres, D. ; Larios, A. ; Guzman, M.
Author_Institution
Nat. Polytech. Inst., CINVESTAV-IPN, Mexico City, Mexico
Volume
1
fYear
1999
fDate
36342
Firstpage
427
Abstract
This paper presents the design for a routing table circuit for Ethernet-, IP- and ATM-applications. The block architecture is explained. Selection principles of the hardware-implemented algorithm for the routing table circuit control are explained, such as a modified trie with its operations in order to achieve a high performance. The circuit, which can support a flow of 400 Mbps, is connected to the PCI bus and stores 64 K addresses. For the implementation a FLEX10K100 from Altera Company was used
Keywords
asynchronous transfer mode; local area networks; packet switching; programmable logic devices; telecommunication network routing; 400 Mbit/s; ATM; Altera FLEX10K100; Ethernet; IP; PCI bus; modified trie; routing chip; routing table circuit; Algorithm design and analysis; Asynchronous transfer mode; Buffer storage; Circuits; Ethernet networks; Hardware; Packet switching; Prototypes; Routing; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.777900
Filename
777900
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