PARC: a new pyramidal FPGA architecture based on a RISC processor

Author

Rabel, C.E. ; Sawan, M.

Author_Institution

Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada

Volume

1

fYear

1999

fDate

36342

Firstpage

470

Abstract

This paper presents a new pyramidal architecture FPGA intended for fast dynamic configurations (PARC) and highly efficient medium design implementation. This device consists of a large number of fine-grained arrays of optimized heterogeneous logic blocks and a new pyramidal structure with three hierarchical levels. In addition, either logic blocks and/or I/O blocks are simplified in order to highly accelerate the routing process which is performed by a controller. The PARC device is a reprogrammable SRAM based product developed with Synopsys design automation CAD tools, using VHDL and the 0.8 μm BiCMOS cell library from Nortel, to operate at a 50 MHz clock frequency. These various features allow for very fast routing-speed improvement when compared to the XC4003A from Xilinx company

Keywords

BiCMOS logic circuits; clocks; field programmable gate arrays; hardware description languages; logic CAD; network routing; reduced instruction set computing; 0.8 micron; 50 MHz; BiCMOS cell library; Nortel; RISC processor; Synopsys design automation CAD tools; VHDL; clock frequency; dynamic configurations; fine-grained arrays; hierarchical levels; optimized heterogeneous logic blocks; pyramidal FPGA architecture; routing process; routing-speed improvement; Acceleration; Automatic control; BiCMOS integrated circuits; Design automation; Field programmable gate arrays; Logic arrays; Logic devices; Random access memory; Reduced instruction set computing; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.777927

Filename

777927