A routability and performance driven technology mapping algorithm for LUT based FPGA designs

This paper presents a CAD technology mapping algorithm, called Wmap, for k-LUT based FPGAs. Wmap is designed to optimize both routability and performance, giving priority to routability. Since interconnection in a FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. Thus, the primary goal of Wmap is the production of a design with a minimum total wire number. After a routable design has been generated, performance is then optimized from the remaining degrees of freedom. The min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that every cluster can be implemented by a CLB in the FPGA and so that the total number of interconnection wires is minimum. Without increasing the number of wires needed, the clusters are then merged into larger clusters by using an existing labeling algorithm that optimizes the performance of the generated network. Finally, CLBs are further merged to minimize the total number of CLBs. This algorithm has been tested on the MCNC benchmark circuits. Compared with the result of a widely used algorithm that considers performance only, Wmap produces a result that uses about 20% less interconnection wires with almost the same number of CLBs. However, assigning optimization priority to interconnections thereby compromises the performance (delay) of the CLB network, yielding a trade-off loss of 15% worse performance than the approximately optimal performance result as determined by DAG-map