DocumentCode
341514
Title
Effective power and ground distribution scheme for deep submicron high speed VLSI circuits
Author
Zheng, L.-R. ; Tenhunen, H.
Author_Institution
Dept. of Electron., R. Inst. of Technol., Stockholm, Sweden
Volume
1
fYear
1999
fDate
36342
Firstpage
537
Abstract
This paper studies the power and ground distribution and its noise effect for deep submicron CMOS VLSI circuits. It is found that orders of magnitude reduction in switching noise can be achieved using an effective power and ground distribution scheme introduced in this paper
Keywords
CMOS digital integrated circuits; VLSI; distributed parameter networks; high-speed integrated circuits; integrated circuit layout; integrated circuit noise; network routing; CMOS VLSI circuits; deep submicron VLSI circuits; ground distribution scheme; high speed VLSI circuits; noise effect; power distribution scheme; switching noise reduction; Circuit noise; Clocks; Integrated circuit noise; MOS capacitors; Noise reduction; Power generation; Switching circuits; Very large scale integration; Voltage; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.777947
Filename
777947
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