A new technique for suppressing reference leakages in phase locked loop

This paper introduces a sample and hold technique for reducing Reference leakages in Phase locked frequency synthesizers without decreasing loop filter band width. A sample and hold circuit is introduced between charge pump and reference leakage filter, obviating the need for decreasing the reference leakage filter band width to suppress the reference leakages. Simulation has been done using System view software, a 840MHz to 1000MHz PLL circuit is designed and simulated in system view software with and without sample and hold circuit. The output plot at VCO control voltage and output spectrum were seen and it was observed that the ripples which were present due to reference leakages in the control voltage were suppressed completely by using sample and hold circuit.