Parallel configuration of oscillator for strong harmonics suppression and frequency doubler

In this paper, a low noise parallel feedback oscillator for harmonic suppression and a frequency doubler are presented. In the oscillator design, as the fundamental signal is extracted between the dielectric resonator (DR) filter and the gate of the active device, the undesired harmonics at the output of the oscillator are remarkably suppressed. The fundamental signal of the oscillator directly feeds to the frequency doubler without an additional band pass filter to suppress spurious harmonics. The second harmonic suppression of -47.7 dBc at the single oscillator output and the fundamental suppression of -37.5 dBc at the frequency doubler output are achieved, respectably.