Estimation of switching noise on power supply lines in deep sub-micron CMOS circuits

To achieve high performance and high integration density, the transistor dimensions are aggressively scaled down while lower power dissipation is achieved by scaling down the supply voltage. However, power distribution has become a challenging issue due to the severe switching noise on the power distribution network. Estimation of the worst case switching noise is essential to ensure the proper functionality of the VLSI circuits. In this paper, we propose a probabilistic approach to determine the lower bound of the worst case switching noise on power supply lines. The proposed algorithm traces the worst case input patterns which will induce the steepest maximum switching current spike and therefore the maximum switching noise. The worst case input patterns are used in the HSPICE simulation to extract the exact switching current waveforms. The estimated maximum switching current spike matches well with the peak current obtained from the HSPICE simulation. The worst case switching noise due to the lumped inductance (including the packaging inductance) and the lumped resistance on the power supply grid is also extracted from the HSPICE simulation. The magnitude of the worst case switching noise for the benchmark circuits implemented with 0.25 μm technology can be as high as 35% of the Vdd. The switching noise can be suppressed effectively with properly placed decoupling capacitors