Stripline Simulation Model with Tapered Cross Section and Conductor Surface Profile

Author

Scogna, A. Ciccomancini ; Schauer, M.

Author_Institution

CST of America Inc., Wellesley Hills

fYear

2007

fDate

9-13 July 2007

Firstpage

1

Lastpage

5

Abstract

The present paper investigates the sensitivity of on wafer interconnect to the Si CMOS process parameters. In particular the tapered (trapezoid) etching and the conductor surface profile (Rrms) of copper foils are numerically analyzed in order to quantify their effect on the electrical performance of a stripline structure. Line impedance, insertion loss and time signal attenuation are evaluated by means of three dimensional (3D) electromagnetic (EM) simulations. Hammerstad and Jensen analytical model is implemented and results are compared with those coming from the full 3D EM simulation model. Good agreement in the frequency range 0- 50 GHz is observed.

Keywords

CMOS integrated circuits; MIMIC; MMIC; UHF integrated circuits; conductors (electric); etching; numerical analysis; 3D EM simulation model; CMOS process parameters; Hammerstad-Jensen analytical model; conductor surface profile; copper foils; electromagnetic simulations; insertion loss; line impedance; numerical analysis; stripline simulation model; tapered cross section; tapered etching; time signal attenuation; Analytical models; CMOS process; Conductors; Copper; Etching; Insertion loss; Performance analysis; Semiconductor device modeling; Stripline; Surface impedance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility, 2007. EMC 2007. IEEE International Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-1349-4

Electronic_ISBN

1-4244-1350-8

Type

conf

DOI

10.1109/ISEMC.2007.147

Filename

4305727