Small-scaled neuro-hardware using probabilistically-coded pulse neurons with on-chip learning

An architecture of a neuro-hardware that can be realized on by far a small-scaled circuit compared to the conventional approach is proposed. In order to reduce the scale of the circuits, the architecture employs a new method of computing the membrane potential and the sigmoidal function by encapsulating the probability properties into relative delay between two pulses. In this architecture, the derivative of sigmoidal function also obtained probabilistically, which enables on-chip learning equipped with back-propagation rule.