Investigation on ESD Transient Immunity of Integrated Circuits

Author

Lacrampe, N. ; Alaeldine, A. ; Caignet, Fabrice ; Perdriau, Richard

Author_Institution

Univ. de Toulouse, Toulouse

fYear

2007

fDate

9-13 July 2007

Firstpage

1

Lastpage

5

Abstract

This paper presents a measurement methodology aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. In our application, a very fast transmission line pulsing (VF-TLP) test bench is used to inject a disturbance into an IC under operation. For simulation purposes, each part of the test bench is modeled separately, and these models are assembled in order to obtain a complete model representing both the injection set-up and the IC itself. The suggested injection model is validated thanks to correlations between measurements and simulations on a full- custom 0.18 mum CMOS IC.

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit noise; integrated circuit testing; transmission lines; CMOS IC; ESD transient immunity; VF-TLP test bench; electrostatic discharge stresses; injection model; integrated circuits; size 0.18 mum; very fast transmission line pulsing; Circuit testing; Electrostatic discharge; Electrostatic measurements; Integrated circuit measurements; Integrated circuit modeling; Integrated circuit testing; Power system transients; Semiconductor device modeling; Stress measurement; Transmission line measurements;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility, 2007. EMC 2007. IEEE International Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

1-4244-1349-4

Electronic_ISBN

1-4244-1350-8

Type

conf

DOI

10.1109/ISEMC.2007.162

Filename

4305742