Efficient VLSI architecture for 2-D inverse discrete wavelet transforms

Author

Yu, Chu ; Chen, Sao-Jie

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

3

fYear

1999

fDate

36342

Firstpage

524

Abstract

In this paper, we present a high-performance VLSI architecture for 2-D inverse discrete wavelet transforms (IDWT). The architecture is designed based on a computation-schedule scheme to process the input signals in real-time, and uses two efficient filter structures to minimize the hardware cost. For the computation of an N×N 2-D image with a filter length L, this architecture spends nearly N² clock cycles, and requires about NL storage unit, 3½L multipliers, as well as 7(L/2-1)+4 adders

Keywords

VLSI; digital arithmetic; digital filters; digital signal processing chips; discrete wavelet transforms; image processing equipment; performance evaluation; real-time systems; signal reconstruction; video signal processing; 2D image processing; 2D inverse DWT; DSP chip; IDWT; VLSI architecture; adders; computation-schedule scheme; filter structures; high-performance architecture; inverse discrete wavelet transforms; multipliers; real-time processing; Clocks; Computer architecture; Costs; Discrete wavelet transforms; Filters; Hardware; Image storage; Signal design; Signal processing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.778898

Filename

778898