• DocumentCode
    3418777
  • Title

    Efficient method of input variable partitioning in functional decomposition based on evolutionary algorithms

  • Author

    Rawski, Mariusz ; Selvaraj, Henry ; Morawiecki, Pawel

  • Author_Institution
    Inst. of Telecommun., Warsaw Univ. of Technol., Poland
  • fYear
    2004
  • fDate
    31 Aug.-3 Sept. 2004
  • Firstpage
    136
  • Lastpage
    143
  • Abstract
    In recent years the functional decomposition has found an application in many fields of modern engineering and science, such as combinational and sequential logic synthesis for VLSI systems, pattern analysis, knowledge discovery, machine learning, decision systems, data bases, data mining etc. However, the lack of an effective and efficient method of the input variable partitioning limits its practical usefulness in complex systems. A classical method based on a systematic search of the whole solution space is inefficient due to its nonpolynomial time complexity. In this paper, a heuristic method for the input variable partitioning is proposed and discussed. The method is based on the application of evolutionary algorithms that allows exploring the possible solution space of a problem while keeping the high-quality solutions in this reduced space. The experimental results show that the proposed heuristic method is able to construct an optimal or near optimal solution very efficiently even for large systems. It is much faster than the systematic method while delivering results of comparable quality.
  • Keywords
    computational complexity; evolutionary computation; heuristic programming; high level synthesis; logic design; VLSI systems; combinational logic synthesis; data mining; databases; decision systems; evolutionary algorithm; functional decomposition; heuristic method; input variable partitioning; knowledge discovery; machine learning; nonpolynomial time complexity; pattern analysis; sequential logic synthesis; CMOS logic circuits; CMOS technology; Digital circuits; Evolutionary computation; Input variables; Logic design; Machine learning; Microelectronics; Network synthesis; Productivity;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital System Design, 2004. DSD 2004. Euromicro Symposium on
  • Print_ISBN
    0-7695-2203-3
  • Type

    conf

  • DOI
    10.1109/DSD.2004.1333269
  • Filename
    1333269