20 GHz feedback amplifier design in standard 0.18 /spl mu/m CMOS

Author

Frank, B.M. ; Freundorfer, A.P. ; Antar, Y.M.M.

Author_Institution

Dept. of Electr. & Comput. Eng., Queen´s Univ., Canada

fYear

2003

fDate

11-11 April 2003

Firstpage

88

Lastpage

91

Abstract

The design of feedback networks for high frequency CMOS amplifiers is presented. It is shown that transistor Y-parameters can be used to design high speed CMOS amplifiers with parallel and series feedback networks to improve the maximum available gain and stability. Single-stage common gate amplifiers fabricated in a standard commercial 0.18 /spl mu/m CMOS process are presented at 20 and 23 GHz. The 20 GHz version offers 6 dB of gain and the 23 GHz version offers 3 dB gain.

Keywords

CMOS analogue integrated circuits; HF amplifiers; feedback amplifiers; high-speed integrated circuits; 0.18 micron; 20 GHz; 23 GHz; 3 dB; 6 dB; CMOS feedback amplifier; feedback network design; high-frequency amplifier; high-speed amplifier; single-stage common gate amplifier; transistor Y-parameters; Capacitors; Clocks; Equations; Feedback amplifiers; Gain; Image analysis; Intelligent networks; Scattering parameters; Stability; Transmission lines;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems, 2003. Digest of Papers. 2003 Topical Meeting on

Conference_Location

Grainau, Germany

Print_ISBN

0-7803-7787-7

Type

conf

DOI

10.1109/SMIC.2003.1196676

Filename

1196676