A reliability-aware design methodology for Networks-on-Chip applications

Network reliability is a key design issue that impacts the performance of all Networks-on-Chip-based systems. In this paper, we develop two reliability models for on-chip interconnection networks using both deterministic and probabilistic measures. Graph-theoretic concepts are adopted with modifications to obtain application-specific reliability models for nine regular network topologies. Using these models, a new methodology is proposed to improve the network reliability of any target application using a topology-based design approach. To validate the effectiveness of the proposed methodology, a case study was performed using an MPEG4 video application. The results were promising and proved that the proposed methodology helps designers better evaluate the impact of their network architecture on the system reliability and assists them in choosing the most appropriate architecture for a target application at early design phases.