Parallel exact critical path tracing fault simulation with reduced memory requirements

A new method based on the critical path tracing is proposed for fault simulation in combinational parts of digital systems. The novelty of the method lays in the possibility to carry out complex computations on sets of faults in parallel simultaneously for many test patterns. A topological analysis is carried out to generate an efficient optimized model for backtracing of faults. Thanks to the parallelism and optimization of the model, the speed of simulation was considerably increased. To overcome the problem of required memory in the case of very large circuits for storing the model, a method of splitting it and the process of parallel reasoning into a number of iterations was proposed. Compared to the state-of-the-art commercial fault simulators the gain in speed was several times.