A ΣΔ modulator for low power energy meter application

The design of a third-order single-bit discrete-time ΣΔ modulator for low-power energy meter application is presented. The modulator employs an input feed-forward topology in order to reduce internal signal swings, thus relaxes the linearity and slew rate requirements on amplifiers. A partially switched amplifier is utilized in the first integrators for low-power consumption. The circuits, simulated at the transistor level using a 0.13-μm CMOS process, obtains a peak SNDR of 99dB over an input signal bandwidth of 14-kHz. The simulated power consumption is 316μW with a 1.2-V supply voltage at a 3.584MHz sampling clock.