• DocumentCode
    3421421
  • Title

    Delay and power consumption of static bulk-CMOS gates using independent bodies

  • Author

    Guerrero, D. ; Millan, A. ; Juan, J. ; Bellido, M.J. ; Clavijo, P. Ruiz-de ; Ostua, E.

  • Author_Institution
    Electron. Technol. Dept., Univ. of Seville, Sevilla
  • fYear
    2009
  • fDate
    6-9 April 2009
  • Firstpage
    191
  • Lastpage
    196
  • Abstract
    Digital designs implemented using SOI processes employ separated bodies for each transistor. This approach is not usually considered in digital bulk-CMOS design because of its obvious area penalty. However, the advantages obtained can justify its utilization in selected parts of the circuits. This is discussed in this paper.
  • Keywords
    CMOS logic circuits; delays; logic design; logic gates; silicon-on-insulator; SOI process; circuit delay; digital design; logic gates; static bulk-CMOS gate; Delay; Energy consumption;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Technology of Integrated Systems in Nanoscal Era, 2009. DTIS '09. 4th International Conference on
  • Conference_Location
    Cairo
  • Print_ISBN
    978-1-4244-4320-8
  • Electronic_ISBN
    978-1-4244-4321-5
  • Type

    conf

  • DOI
    10.1109/DTIS.2009.4938053
  • Filename
    4938053
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3421421