DocumentCode
3422200
Title
Memory reference metrics and instruction trace sampling
Author
Kabayashi, Mitsuru
Author_Institution
Apple Comput. Inc., Cupertino, CA
fYear
1997
fDate
5-7 Feb 1997
Firstpage
301
Lastpage
307
Abstract
Trace-driven simulation models have been widely used to accurately estimate performance of proposed microarchitectures. Accuracy of the estimated performance greatly depends on the instruction traces as well as the model itself. Although long instruction traces are preferred, e.g. to fill a large cache, a trace could often be redundantly long; it might merely represent a small, tight loop. In this paper we try to select representative samples from a given trace consisting of multiple samples. We introduce three new metrics for memory references: the Access Scatter Function, the Block Execution Interval, and the Local Execution Intervals. These new metrics and basic block sizes, branch distances, execution intervals, and the Stack Growth Function are used to characterize each sample. Then, samples are clustered to select representative samples. Analysis of two real instruction traces of batch and database workloads in a large mainframe is shown as an example
Keywords
discrete event simulation; instruction sets; parallel architectures; Access Scatter Function; Block Execution Interval; Local Execution Intervals; branch distances; database workloads; execution intervals; instruction trace sampling; instruction traces; memory reference metrics; microarchitectures; trace-driven simulation models; Computational modeling; Computer simulation; Databases; Memory management; Microarchitecture; Operating systems; Pipelines; Registers; Sampling methods; Scattering;
fLanguage
English
Publisher
ieee
Conference_Titel
Performance, Computing, and Communications Conference, 1997. IPCCC 1997., IEEE International
Conference_Location
Phoenix, Tempe, AZ
Print_ISBN
0-7803-3873-1
Type
conf
DOI
10.1109/PCCC.1997.581531
Filename
581531
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