DocumentCode
3424044
Title
Lattice filter implementation with ETSI math operations on the TMS320C62xx
Author
Buvaneswari, A. ; Haner, Mark
Author_Institution
Lucent Technol. Bell Labs., Murray Hill, NJ, USA
Volume
2
fYear
2002
fDate
3-6 Nov. 2002
Firstpage
1094
Abstract
The specific lattice filter implementations considered here are the short-term analysis and synthesis filter realizations in the GSM Full Rate (06.10) specifications. With the ETSI math operations like multiply with round (mult-r) to be performed, and with TMS320C62xx´s instruction set not consisting of any mult-r or even round operation, the C-compiler generated code fails to achieve the best performance. With techniques like unrolling the loop, intelligent scheduling of the math operations in the pipeline etc., and hand coding in assembly, we show how to achieve a performance better than that of a processor with operations like mult-r in its instruction set.
Keywords
cellular radio; digital filters; digital signal processing chips; fixed point arithmetic; lattice filters; C-compiler generated code; ETSI math operations; GSM Full Rate specifications; TMS320C62xx; TMS320C62xx processor; assembly; fixed-point DSP; forward lattice filters; hand coding; instruction set; intelligent scheduling; inverse lattice filters; lattice filter implementation; loop unrolling; multiply with round; pipeline; short-term analysis filter; short-term synthesis filter; Digital signal processing; Filtering; Filters; GSM; Lattices; Reflection; Signal synthesis; Speech analysis; Speech synthesis; Telecommunication standards;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2002. Conference Record of the Thirty-Sixth Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-7803-7576-9
Type
conf
DOI
10.1109/ACSSC.2002.1196953
Filename
1196953
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