On modeling and hardware implementation of Space-Time Adaptive Processing (STAP) for target detection in passive BI-static radar

This paper presents the modeling and partial FPGA implementation of Space Time Adaptive Processing (STAP) algorithm for Passive Bi-static Radar (PBR) using commercial FM transmitter as illuminator of opportunity. Two simulated targets were inserted in the real-time recorded FM eight channel data signal. The simulated targets were detected after effective zero Doppler frequency clutter removal with the help of optimum matched filtering. Hardware implementation of STAP processor including phase correction, Doppler frequency correction and Kronecker product is provided and explained. The system was designed and developed using Xilinx FPGA Virtex-6 platform.