• DocumentCode
    3430606
  • Title

    A fault model for function and delay testing

  • Author

    Yi, Joonhwan ; Hayes, John P.

  • Author_Institution
    The University of Michigan
  • fYear
    2001
  • fDate
    May 29 2001-June 1 2001
  • Firstpage
    27
  • Lastpage
    34
  • Abstract
    Existing gate-level fault models are not well suited to test generation for circuits that contain modules whose logic implementation and timing behavior are unspecified. A high-level fault model called the coupling fault (CF) model is presented which aims to cover both functional and timing faults in an integrated manner. Intuitively, a (single) CF denoted xi|zj exists between input xi and output zj of a module if xi|zj blocks any dynamic effect of xi on zj The set of test vectors CTSxi|zj that detect xi|zj is represented by the boolean difference of zj with respect to xi. A pair of adjacent vectors in CTSxi|zj, constitutes a coupling delay test. This article studies the basic properties of coupling faults and test sets, focusing on the relationship between coupling tests and other high-level tests. A coupling test set provides powerjhl, realization-independent coverage of stuck-at faults. Coupling delay tests can detect all robust path delay faults in any realization of afunction.
  • Keywords
    Adders; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Logic gates; Logic testing; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Workshop, 2001. IEEE European
  • Conference_Location
    Stockholm, Sweden
  • ISSN
    1530-1877
  • Print_ISBN
    0-7695-1017-5
  • Type

    conf

  • DOI
    10.1109/ETW.2001.946657
  • Filename
    946657